This invention is in the field of solid-state memory. Embodiments of this invention are more specifically directed to the manufacture and testing of static random access memories (SRAMs).
Many modern electronic devices and systems now include substantial computational capability for controlling and managing a wide range of functions and useful applications. Considering the large amount of digital data often involved in performing the complex functions of these modern devices, significant solid-state memory capacity is now commonly implemented in the electronic circuitry for these systems. Static random access memory (SRAM) has become the memory technology of choice for much of the solid-state data storage requirements in these modern power-conscious electronic systems. As is fundamental in the art, SRAM cells store contents “statically”, in that the stored data state remains latched in each cell so long as power is applied to the memory; this is in contrast to “dynamic” RAM (“DRAM”), in which the data must be periodically refreshed in order to be retained.
Advances in semiconductor technology in recent years have enabled the shrinking of minimum device feature sizes (e.g., MOS transistor gates) into the sub-micron range. This miniaturization is especially beneficial when applied to memory arrays, because of the large proportion of the overall chip area often devoted to on-chip memories. As a result, significant memory resources are now often integrated as embedded memory into larger-scale integrated circuits, such as microprocessors, digital signal processors, and “system-on-a-chip” integrated circuits. However, this physical scaling of device sizes raises significant issues, especially in connection with embedded SRAM but also in SRAM realized as “stand-alone” memory integrated circuit devices. Several of these issues are due to increased variability in the electrical characteristics of transistors formed at these extremely small feature sizes. This variability in characteristics has been observed to increase the likelihood of read and write functional failures, on a cell-to-cell basis. Sensitivity to device variability is especially high in those memories that are at or near their circuit design limits. The combination of increased device variability with the larger number of memory cells (and thus transistors) within an integrated circuit renders a high likelihood that one or more cells cannot be read or written as expected.
An example of a conventional SRAM cell is shown in FIG. 1a. In this example, SRAM cell 2 is a conventional six-transistor (6-T) static memory cell 2, which in this case is in the jth row and kth column of a memory array. SRAM memory cell 2 is biased between the voltage on power supply line Vdda and a ground reference voltage Vssa. SRAM memory cell 2 is constructed in the conventional manner as a pair of cross-coupled CMOS inverters, one inverter of series-connected p-channel load transistor 3a and n-channel driver transistor 4a, and the other inverter of series-connected p-channel load transistor 3b and n-channel transistor 4b; the gates of the transistors in each inverter are connected together and to the common drain node of the transistors in the other inverter, in the usual manner. The common drain node of transistors 3a, 4a constitutes storage node SNT, and the common drain node of transistors 3b, 4b constitutes storage node SNB, in this example. N-channel pass-gate transistor 5a has its source/drain path connected between storage node SNT and bit line BLTk for the kth column, and n-channel pass-gate transistor 5b has its source/drain path connected between storage node SNB and bit line BLBk. The gates of pass-gate transistors 5a, 5b are driven by word line WLj for this jth row in which cell 2 resides.
In operation, bit lines BLTk, BLBk are typically precharged by precharge circuitry 7 to a high voltage Vddp (which is at or near power supply voltage Vdda) and are equalized to that voltage; precharge circuitry 7 then releases bit lines BLTk, BLBk to then float during the remainder of the access cycle. To access cell 2 for a read operation, word line WLj is then energized, turning on pass-gate transistors 5a, 5b, and connecting storage nodes SNT, SNB to bit lines BLTk, BLBk. The differential voltage developed on bit lines BLTk, BLBk is then sensed and amplified by a sense amplifier. In a write operation, typical modern SRAM memories include write circuitry that pulls one of bit lines BLTk, BLBk low (i.e., to a voltage at or near ground voltage Vssa), depending on the data state to be written. Upon word line WLj then being energized, the low level bit line BLTk or BLBk will pull down its associated storage node SNT, SNB, causing the cross-coupled inverters of addressed cell 2 to latch in the desired state.
As mentioned above, device variability and other factors can cause read and write failures, particularly in memory cells constructed with sub-micron minimum feature size transistors. A write failure occurs when an addressed SRAM cell does not change its stored state when written with the opposite data state. Typically, this failure has been observed to be due to the inability of write circuitry to pull down the storage node currently latched to a high voltage. For example, in an attempt to write a low logic level to storage node SNT of cell 2 of FIG. 1a, if bit line BLTk is unable to sufficiently discharge storage node SNT to a sufficient level to trip the inverters, cell 2 may not latch to the desired data state. One cause of a write failure is weakness in the drive of a pass transistors (transistors 5a, 5b of cell 2). For the example in which cell 2 of FIG. 1a is initially storing a “0” state (storage node SNT held low by driver transistor 4a in its on state), a write of the opposite “1” state is performed by bit line BLBk being pulled low while word line WLj is energized. If the drive of pass transistor 5b is weak, storage node SNB will tend to remain at a high level despite the low level of bit line BLBk. The apparent trip voltage Vtrip at bit line BLBk that actually causes a successful write will thus be lower than optimal, due to the weakness of pass transistor 5b. It has been observed that write failures (i.e., the measure Vtrip) has a worst case at low temperature.
Cell stability failures are the converse of write failures—while a write failure occurs if a cell is too stubborn in changing its state, a cell stability failure occurs if a cell changes its state too easily during a read. A cell stability failure also occurs if a write to a selected memory cell causes a false write of data to unselected cells in that same row (i.e., to the “half-selected” cells in unselected columns of the selected row). The possibility of such stability failures is exacerbated by device mismatch and variability, as discussed above.
A useful quantitative measure of cell stability is referred to as static noise margin (SNM), which corresponds to the noise at a storage node that the cell can tolerate without changing its logic state, and can be approximated by the area of the largest square that fits between transfer characteristics for the two state transitions. In the familiar fashion, the butterfly curves of FIG. 1b illustrate the voltages at storage nodes SNT, SNB of cell 2 in their two potential data states, and transitions between the two. In this example, the “1” data state is at stable point DS1 at which voltage VSNT at storage node SNT is near power supply voltage Vdda and voltage VSNB at storage node SNB is near ground (Vssa); conversely, the “0” data state is at stable point DS0, with voltage VSNB near power supply voltage Vdda and voltage VSNT near ground. Transfer characteristic TF1-0 shows the voltages at storage nodes SNT, SNB for a transition from stable point DS1 to stable point DS0 (a “1” to “0” transition). Transfer characteristic TF0-1 similarly shows the voltages at storage nodes SNT, SNB for the transition from stable point DS0 to stable point DS1 (a “0” to “1” transition). FIG. 1b illustrates static noise margin SNM for SRAM cell 2 as the area of the largest square that fits between transfer characteristics TF1-0, TF0-1.
Cell stability failures (i.e., insufficient static noise margin) can occur in cases in which the drive of the SRAM cell driver transistors (transistors 4a, 4b of cell 2 in FIG. 1a) is mismatched, with one driver transistor having decreased drive relative to its associated pass transistor (transistors 5a, 5b, respectively). For the example in which cell 2 of FIG. 1a is storing a “0” state (storage node SNT low), if driver transistor 4a has weakened drive relative to its pass transistor 5a, the voltage divider of these two devices when on in a read cycle will reflect a higher than optimal voltage at storage node SNT; this higher voltage will tend to turn driver transistor 4b on, which would flip the state of cell 2. It has been observed that cell stability has a worst case at high temperature.
The level of reliability required of integrated circuits has increased to new heights in recent years, especially in certain applications such as automotive systems. This enhanced reliability level has increased the extent to which integrated circuit manufacturers implement time-zero screens to remove (or repair, by way of redundant memory cells and circuit functions) those devices that are vulnerable to failure over the expected operating life of the device. A conventional approach in such screening is to apply “guardbands” on certain applied voltages during functional or parametric tests of circuit functions. In many cases, guardbanded voltages are implemented to account for the temperature dependence of circuit behavior, to enable the manufacturer to perform functional testing at one temperature (preferably room temperature) with confidence that the circuit will perform according to specification over the full specified temperature range, over the expected operating life. As known in the art, it is becoming increasingly difficult to design the appropriate test “vectors” (i.e., combinations of bias and internal circuit voltages, and other test conditions) that identify devices that are vulnerable to failure over time and temperature, without significant yield loss of devices that would not fail over operating life yet fail the screen at the applied guardbanded test vectors.
This difficulty is exacerbated by transistor degradation mechanisms that have become observable at the extremely small minimum feature sizes in modern integrated circuits. An important mechanism in this regard is negative bias temperature instability (“NBTI”), which appears as an increase in threshold voltage over time, primarily in p-channel MOS transistors. In the context of CMOS SRAMs, NBTI degradation affects the ability of memory cells to store and retain data. Conventional manufacturing test flows for sub-micron CMOS SRAMs now commonly include screens to identify (or invoke repair via redundant rows or columns) memory cells that are close to a pass/fail threshold at manufacture, within a margin corresponding to the expected NBTI drift over the desired operating life.
Copending U.S. application Ser. No. 13/189,675, filed Jul. 25, 2011, commonly assigned herewith and incorporated herein by reference, describes a screening method for testing solid-state memories for the effects of long-term shift due to NBTI in combination with random telegraph noise (RTN), in the context of SRAM cells As described in that application, each memory cell in the array is functionally tested with a bias voltage (e.g., the cell power supply voltage) at a first guardband that is sufficient to account for worst case long-term shift and RTN effects. Cells failing the first guardband test are then repeatedly tested with the bias voltage at a second guardband that is less severe than the first; those previously failed cells that pass this second guardband are considered to not be vulnerable to RTN effects. This approach avoids the over-screening of conventional test methods that apply an unduly severe guardband, while still identifying vulnerable memory cells in the population for repair or as failed devices.
By way of further background, it is known in the art to apply a voltage higher than the power supply voltage to the body nodes of the p-channel load transistors during the test of SRAM arrays. This condition is referred to in the art as a “reverse back-bias” condition, and is typically applied to the n-well regions in which the load transistors are formed. As fundamental in the art, this reverse back-bias voltage has the effect of increasing the threshold voltage of the load transistors, and thus reducing their source-drain drive at a given source-drain voltage and gate-source voltage. Such a test is performed with the intent of screening out cells that are vulnerable to increased threshold voltage over operating time caused by NBTI.
Positive bias-temperature instability (“PBTI”) refers to a similar degradation effect that primarily affects n-channel MOS transistors. It has been observed, however, that degradation due to PBTI of n-channel transistors with silicon dioxide gate dielectrics is very slight, especially as compared to the NBTI degradation of p-channel transistors in the same circuits. As such, PBTI is typically not a significant reliability concern in conventional gate oxide technologies.
Recently, however, the continuing demand for ever-smaller device geometries has led to the more widespread use of high-k gate dielectric films (i.e., gate dielectric materials with a high dielectric constant relative to that of silicon dioxide). These high-k gate dielectric films, which enable the formation of thicker gate dielectrics with excellent gate characteristics, are typically used in conjunction with metal gate electrodes, rather than polysilicon gates, due to such effects as polysilicon depletion. A common high-k dielectric film used in the art is hafnium oxide (HfO2). Examples of the metal gate material in modern device technologies include titanium nitride (TiN), tantalum-silicon-nitride (TaxSiyN), and tantalum carbide (TaCx).
It has been observed, however, that high-k metal gate n-channel MOS transistors are vulnerable to threshold voltage shifts due to PBTI, even though their conventional gate dielectric n-channel devices are not. This vulnerability is believed due to the affinity of HfO2 films to trap electrons under positive gate bias (relative to the transistor channel region). As in the case of NBTI, the effect of PBTI on high-k metal gate n-channel MOS transistors is an increase in threshold voltage over time. And PBTI degradation of the n-channel cell transistors can cause read current failures in read cycles, in which weakened read current causes an insufficient differential signal to be developed across bit lines and results in an incorrect data state being read.
It has been discovered, in connection with this invention, that it is difficult to derive an accurate time-zero screen to identify those memory cells (i.e., constructed in high-k metal gate n-channel MOS) for which PBTI degradation will cause write failures, cell stability failures, or read current failures. To the extent that potential proxies for this effect are available, modern reliability goals may require an excessively harsh screen margin (e.g., guardband voltages above the maximum operating voltages) that itself may degrade long-term reliability. In addition, the undue yield loss of devices that fail such a screen but would, in fact, not have degraded to failure, can be substantial.
By way of further background, copending U.S. application Ser. No. 13/196,010, filed Aug. 2, 2011, entitled “SRAM Cell Having a P-Well Bias”, commonly assigned herewith and incorporated herein by reference, describes a CMOS SRAM cell in which the complementary n-channel MOS driver transistors are constructed in p-type wells that are isolated from one another. The n-channel pass transistors may be also constructed in respective isolated p-wells, or may each share a p-well with one of the driver transistors. This application also describes performing operations in which one or more of the isolated p-wells for the driver transistors are more negatively biased during read cycles. Positive bias applied to the isolated p-wells for one or more of the pass transistors in write cycles is also disclosed.
By way of further background, copending U.S. application Ser. No. 13/220,104, filed Aug. 29, 2011, entitled “Method of Screening Static Random Access Memories for Pass Transistor Defects”, commonly assigned herewith and incorporated herein by reference, describes a method of screening SRAM arrays to identify memory cells with bit line side pass transistor defects. After writing a known data state to the memory cells under test, a forward back-bias is applied to the load transistors of those cells, to reduce the load transistor threshold voltage. This forward back-bias is applied by raising the voltage of the n-well in which the p-channel load transistors are formed, above the voltage at the source nodes of those transistors, which strengthens the drive of the “on” load transistor (for the stored data state). A write of the opposite data state is then performed, followed by a read of the memory cells. The increased load transistor drive during write will tend to cause write failures for those cells having a pass transistor with weakened drive due to a bit line side defect.